The present invention relates to random access memories and in particular to a dual port random access memory which permits two data processing devices to read or write access the memory at the same time.
In many applications more than one data processing device competes for read or write access to the same random access memory. For example, in a high speed computer system, a direct memory access (DMA) controller may be capable of reading sequences of data stored in a memory and placing that data on a system input/output bus, and may also be capable of acquiring data on the input/output bus and storing that data in the memory. Such memory access may be performed by the DMA controller at the same time that a central processor of the computer is performing other operations. However, since the processor must also have read and write access to the memory, the processor may be restricted to performing operations which do not involve memory access when the DMA controller is accessing the memory. Inasmuch as processors access memory frequently, such a restriction can adversely affect system performance. Dual memories have been developed which permit more than one data processing device to access data at different storage locations at the same time. But during a write operation data must be written into corresponding cells of both memories, and such dual memories have relatively longer memory access times than comparable single memories due to increased input capacitance seen by input data and control signals, and this capacitance must be charged or discharged in order to effect a change of state of the stored data.